The present invention relates to a semiconductor memory device, and more particularly, to a delay locked loop of a semiconductor memory device.
A semiconductor memory device serves to store data in a system which includes plural semiconductor devices. When a data processing device, e.g., a central processing unit (CPU), requires a data, the semiconductor memory device outputs a data corresponding to an address input by the data requiring device or stores a data received from the data requiring device into memory cells corresponding to the address.
As the operational speed of systems increases and semiconductor integrating technology matures, semiconductor memory devices are required to perform data access operations at higher speed. For performing the data access operation at high speed, synchronous memory devices have been developed for performing data access operations in synchronization with a clock.
To further improve the operational speed of synchronous memory devices, double data rate (DDR) synchronous memory devices have been developed for performing data access operations in synchronization with both the rising and falling edges of a clock.
Since a DDR synchronous memory device inputs or outputs data in synchronization with both the rising and falling edges of the clock, the DDR synchronous memory device should process two pieces of data within one period of the system clock. That is, the DDR synchronous memory device should output a data or store a data at a rising edge and a falling edge of the clock.
Particularly, the output of data from the DDR synchronous memory device should be exactly synchronized with a rising edge or a falling edge of the clock. For this, a data output circuit of the DDR synchronous memory device outputs data in synchronization with a rising edge and a falling edge of the system clock.
However, the clock input for a semiconductor memory device is inevitably delayed as the clock passes through internal units of the semiconductor memory device, e.g., a clock input buffer or a transfer line for transferring a clock signal. If the data output circuit outputs data in synchronization with the delayed clock, an external data requiring device receives data which is not synchronized with its respective rising or falling edge of the clock.
For solving the above-mentioned problem, a semiconductor memory device includes a delay locked loop. The DLL serves to compensate for a delay amount generated while the clock is transferred to the data output clock after the clock is input to the semiconductor memory device.
The DLL detects a delay amount generated while the system clock is transferred through the clock input buffer and the clock signal transfer line and delays the system clock corresponding to the detected delay amount to output the delayed system clock to the data output circuit. That is, by the DLL, the system clock input to the semiconductor memory device is transferred to the data output circuit with being delay-locked.
The data output circuit outputs data in synchronization with the delay locked clock and, thus, an external device receives data that is output in synchronization with the clock. In an actual operation, the delay locked clock output from the DLL is transferred to an output buffer one cycle prior to a point of time when a data should be output, and data is output in synchronization with the transferred delay locked clock. Therefore, data is output faster than a delay amount of the clock generated by internal circuits of the semiconductor memory device while the clock is transferred through the semiconductor memory device.
In this manner, data can be output from a semiconductor memory device in synchronization with a rising edge and a falling edge of a clock input to the semiconductor memory device. As a result, a delay locked loop serves to detect how much faster data should be output in order to compensate for a delay amount of the clock.
FIG. 1 is a block diagram showing a conventional delay locked loop (DLL) for use in a semiconductor memory device.
The DLL includes a phase comparison unit 10, a charge pump 20, a loop filter 30, a delay line 40 and a lock detector 50.
The phase comparison unit 10 compares each phase of two inputted clock signals CLKS and CLKD in order to output a signal which corresponds to the comparison signal. The charge pump 20 supplies a quantity of charge corresponding to the output signal of the phase comparison unit 10. The loop filter 30 generates a voltage corresponding to the charge quantity supplied by the charge pump 20.
The delay line 40 delays the clock signal CLKS by a delay time corresponding to the voltage generated by the loop filter 30 in order to output the delayed signal as the delayed clock signal CLKD. The lock detector 50 outputs a locking signal LOCK to the phase comparison unit 10 when a phase of the clock signal CLKS is the same as that of the delayed clock signal CLKD so that the phase comparison unit 10 is not operated.
When the locking signal LOCK output from the lock detector 50 is active, a delay locking operation of the DLL is finished. As mentioned above, a delay locked clock of the conventional DLL is used as a reference signal for the semiconductor memory device to output data.
As technology develops, the frequency of a clock input to a semiconductor memory device increases more and more. Accordingly, the frequency of a clock signal delayed and locked by a DLL has increased and a period of the clock signal has decreased.
Since the period of the clock signal is decreased, a delay locking operation of the DLL is more difficult. That is, when the period of the clock signal is decreased, even if the clock signal is slightly changed due to external circumstances, a relatively large variation is generated.
When there is only a small difference between each phase of the two clocks CLKS and CLKD, the difference is very large variation in comparison with the period of the clock signal and, thus, it is difficult for the phase comparison unit 10 to compare phases. Therefore, an operation time of the DDL may be greatly increased. Furthermore, since a delay amount of a delay line is fixed, if a phase difference between the two clocks CLKS and CLKD is larger than the delay amount of the delay line, a delay locking is not easily completed.